For some time the semiconductor industry has been using bulk CMOS wafer technology to make integrated circuits. Wafers are diced into individual sections commonly known die or chips, with each chip being packaged into electronic devices. Bulk CMOS technology has proven to be particularly “scalable,” meaning that bulk CMOS transistors can be made smaller and smaller while optimizing and reusing existing manufacturing processes and equipment in order to maintain acceptable production costs. Historically, as the size of a bulk CMOS transistor decreased, so did its power consumption, helping the industry provide increased transistor density and lower operating power. Thus, the semiconductor industry has been able to scale the power consumption of bulk CMOS transistors with their size, reducing the cost of operating transistors and the systems in which they reside.
In recent years, however, decreasing the power consumption of bulk CMOS transistors while reducing their size has become increasingly more difficult. Transistor power consumption directly affects chip power consumption, which, in turn, affects the cost of operating a system and, in some cases, the utility of the system. For example, if the number of transistors in the same chip area doubles while the power consumption per transistor remains the same or increases, the power consumption of the chip will more than double. This is due in part by the need to cool the resulting chip, which also requires more energy. As a result, this would more than double the energy costs charged to the end user for operating the chip. Such increased power consumption could also significantly reduce the usefulness of consumer electronics, for example, by reducing the battery life of mobile devices. It could also have other effects such as increasing heat generation and the need for heat dissipation, potentially decreasing reliability of the system, and negatively impacting the environment.
There has arisen among semiconductor engineers a widespread perception that continued reduction of power consumption of bulk CMOS is not feasible, in part because it is believed that the operating voltage VDD of the transistor can no longer be reduced as transistor size decreases. A CMOS transistor is either on or off. The CMOS transistor's state is determined by the value of a voltage applied to the gate of the transistor relative to a threshold voltage VT of the transistor. While a transistor is switched on, it consumes dynamic power, which can be expressed by the equation:Pdynamic=CVDD2f where VDD is the operating voltage supplied to the transistor, C is the load capacitance of the transistor when it is switched on, and f is the frequency at which the transistor is operated. While a transistor is switched off, it consumes static power, which can be expressed by the equation:Pstatic=IOFFVDD where IOFF is the leakage current when the transistor is switched off. Historically, the industry has reduced transistor power consumption primarily by reducing the operating voltage VDD, which reduces both dynamic and static power.
The ability to reduce the operating voltage VDD depends in part on being able to accurately set the threshold voltage VT, but that has become increasingly difficult as transistor dimensions decrease. For transistors made using bulk CMOS processes, one of the primary parameters that sets the threshold voltage VT is the amount of dopants in the channel. Other factors that affect VT are halo implantation, source and drain low doped extensions, and channel thickness. In theory, matching transistor VT can be done precisely, such that the same transistors on the same chip will have the same VT, but in reality the process and statistical variations in dopant concentration and placement mean that threshold voltages can vary significantly. Such mismatched transistors will not all switch on at the same time in response to the same gate voltage, and in extreme cases some may never switch on. Of even more concern, mismatched transistors result in increased leakage losses that waste power even when a transistor is not actively switching.
For transistors having a channel length of 100 nm or less, as few as thirty to fifty dopant atoms may be positioned in a channel at nominal dopant concentration levels. This compares with the thousands, or tens of thousands of atoms that are in positioned in the channel for previous generation transistors that have channel lengths greater than 100 nanometers or so. For nanometer scale transistors, the inherent statistical variation in numbers and placement of such few dopant atoms results in a detectable variation in VT known as random dopant fluctuations (RDF). Along with process and material variations, for nanometer scale bulk CMOS transistors with doped channel, RDF is a major determinant of variations in VT (typically referred to as sigma VT or σVT) and the amount of σVT caused by RDF only increases as channel length decreases.
Processes and designs for novel transistors having greatly reduced σVT are sought by the industry. However, many proposed solutions such as undoped channel FINFET would require substantial changes in transistor process manufacture and layout. This has slowed adoption, since the industry prefers to avoid redesigns that require substantial change in conventional and widely used integrated circuit manufacturing processes and transistor layout. This is particularly true for Systems on a Chip (SoC) or other highly integrated devices that include a wide variety of circuit types, such as analog input and output circuits (I/O), digital circuits, and other types of circuits. Moreover, given the different types of circuits on such highly integrated systems, if one or more types of circuits can be improved, and any necessary legacy circuits remain the same, the overall SoC should still be produced together to avoid extra steps in the manufacturing process. For example, if an improvement to the digital circuits can be accomplished, and the improvement did not apply to analog circuits, it would be desirable to have the circuits to be manufactured together simultaneously without adding further processing steps. The entire integrated circuit can be redesigned to accommodate operation at the reduced voltage power source. As referenced herein, the term “redesign” can include appropriate sizing of transistor gates prior to circuit fabrication. However, difficulties are encountered when redesign attempts are made. Extra process and masking steps, can be complex, costly and technically difficult.
Given the substantial costs and risks associated with transitioning to a new technology, manufacturers of semiconductors and electronic systems have long sought a way to extend the use of bulk CMOS. At least in part due to the inability to easily control σVT variation in groups of transistors as VDD is substantially reduced below one volt, the continued reduction of power consumption in bulk CMOS has increasingly become viewed in the semiconductor industry as an insurmountable problem.